This invention relates to a frequency synthesizer employing a phase locked loop and an apparatus using the same. Particularly, the invention relates to the configuration of a frequency synthesizer suitable for use in mobile communication equipment which requires high speed switching of communication frequencies.
A variety of frequency synthesizers have been known (refer to V. Manassewitch, "Frequency Synthesizers Theory and Design", pp. 1-39, John Wiley & Sons, New York, 1976), and a configuration employing a phase locked loop has particularly been used with the development of integrated circuits. In mobile communication equipment having a number of communication channels, a voltage controlled oscillator (hereinafter called the "VCO"), a variable dividing counter and a crystal oscillator are used to configure a phase looked loop for selecting a dividing number of the variable dividing counter to generate a necessary communication channel frequency. A signal produced by dividing an output signal from the VCO by the selected dividing number of the variable dividing counter is compared with a reference signal produced by an output signal of the crystal oscillator in phase by a phase comparator, and the comparison result represented by an analog value is integrated by a filter and then applied to a frequency control terminal of the VCO. Since this result of the phase comparator includes harmonic components and, the integration time constant of the filter must be large in order to remove such components. As a result, the capacitance value of a capacitor constituting the filter becomes relatively large. For this reason, if the dividing number of the variable dividing counter is to be changed to switch the communication channel frequency, recharging and discharging of the capacitor requires a long period of time, which incurs a problem that rapid switching of the frequency is hindered.
Considering the fact that the above-stated problem occurs when the phase comparator output is generated in analog form, a configuration of a frequency synthesizer for solving this problem is proposed in "A New PLL Synthesizer for Fast FH Spread Spectrum Communications", by Akihiro and Nakagawa, Globecom, 1989. FIG. 1 shows the circuit configuration, and FIGS. 2A, 3A-3D show the operation principle.
A frequency synthesizer configured as proposed in the above document is called the "numerical phase-comparating and continuous leveling frequency synthesizer system" for convenience. This prior art performs a phase comparison itself by numerical operations and removes harmonic components included in the comparison result by a simple operation to render a filter unnecessary, thus reducing the time necessary to switch the frequency. This frequency synthesizer increases phase information on a reference signal having a period T by 2.pi./K every period given by T/K (K is an integer) as shown in FIG. 2, and supplies a phase comparator with this phase information as a saw-tooth like waveform (FIG. 3A) for resetting the phase comparator every period T. An output signal from the VCO in turn is divided by a modulo N counter having an integer dividing number N, the contents of which are normalized by 2.pi./N and then supplied to the phase comparator as phase information every period T/K (FIG. 3B). The two phase information signals supplied to the phase comparator are numerically subtracted and output from the phase comparator. In this event, even with the frequencies of two signals input to the phase comparator being coincident with each other, if the initial phases of both the phase information signals are not coincident, a phase jump of 2.pi. occurs in the output of the phase comparator (FIG. 3C). In a phase compensator, one side of the phase jump is shifted by 2.pi. to make the phase comparison value constant (FIG. 3D). In this continuous leveling processing, the output E of the phase comparator is subjected to the following mathematical operation to derive a continuous level phase error E': EQU E'=mod{(E+3.pi.), 2.pi.}-.pi.
where mod{A, B} represents a remainder when A is divided by B. This continuous level phase comparison value is converted to an analog value by a digital-to-analog (D/A) convertor and thereafter applied to a frequency control terminal of the VCO. In this event, assuming that a reference signal frequency is at f.sub.r 1, an oscillating frequency f.sub.v of the VCO is expressed by the following Equation 1: EQU f.sub.v =(N/K).multidot.(K.multidot.f.sub.r 1) Equation 1
It will be understood from the foregoing that since the phase comparison value is made constant, the filter is not necessary, which enables fast frequency switching. Also, as K becomes larger, i.e., as the sampling frequency K.multidot.f.sub.r 1 is higher, higher frequency switching is possible.
The existing numerical phase-comparating and continuous leveling frequency synthesizer as described above has a first problem that a large circuit scale is required for the phase compensator which renders constant the output of the phase comparator as shown in FIG. 3D.
Also, in Equation 1 expressing the oscillating frequency of the numerical phase-comparating and continuous leveling frequency synthesizer, with N/K which is not an integer, if the contents of a modulo N counter is sampled at every period T/K, a phase error may be caused by truncating a fraction of N/K. This results in a second problem that a generated frequency does not completely coincide with a predetermined frequency. Assume, for example, that K is equal to eight; and N to 1002, where a constant A is employed instead of 2.pi. and A is equal to 1000 for facilitating digital processing. In this case, a sampled value Ci (i=1-8) of the modulo N counter, a normalized phase value Vi derived by multiplying the sampled value Ci by a constant A/N for normalization, a reference phase value Ri and a phase error Hi are calculated as shown in Table 1.
TABLE 1 __________________________________________________________________________ 2.pi.:1000, K = 8, N = 1002 Sampling Step Signals 1 2 3 4 5 6 7 8 __________________________________________________________________________ Counter output Ci 125 250 375 501 626 751 876 1002 Normalized Phase Value Vi 124.75 249.50 374.25 500.00 624.75 749.50 874.25 1000.0 Ref. Phase Value Ri 125 250 375 500 625 750 875 1000 Phase Error Hi -0.25 -0.50 -0.75 0.0 -0.25 -0.50 -0.75 0.0 __________________________________________________________________________
Here, a state arises, wherein the phase error Hi between the reference phase value Ri and the normalized phase value Vi does not become zero for each sampling, and an average phase error over one period of the phase error Hi does not either become zero. While in Table 1, the normalized phase value Vi and the phase error Hi are shown only up to the third decimal place for simplifying the table, the above state also arises even if these values are expressed in infinite word length. Thus, this type of frequency synthesizer has a problem that an accurate frequency cannot be generated unless N/K is an integer.
When a high frequency signal, which is an output of the VCO, is divided, a prescaler with a dividing number P may be inserted in front of a variable divider in order to decrease the frequency. However, since P is not generally equal to K in this case, the same problem as above arises in terms of the occurrence of a fraction.
Also, the existing numerical phase-comparator and continuous leveling frequency synthesizer employ a constant A instead of the phase 2.pi. of one cycle for facilitating the digital processing and normalize the contents of the modulo N counter with A/N. On the other hand, N is changed to modify the frequency generated by the synthesizer. Therefore, A/N is generally not an integer. Even with the constant A set at a considerably large value, under the condition that N is changed one by one, a majority of the A/N values are not integers. This causes an error in normalized phase information of the counter, thereby incurring a third problem that an accurate frequency cannot be generated.